This invention is in the field of the manufacture of semiconductor integrated circuits. Embodiments of this invention are more specifically directed to the fabrication of isolation structures at the locations of bipolar transistors in semiconductor integrated circuits.
As fundamental in the art, an important parameter related to the performance of bipolar junction transistors is the common-emitter current gain, or forward-active current gain. This parameter is commonly symbolized as β or βF, according to the Ebers-Moll model terminology; in the h-parameter model terminology, the bipolar transistor current gain is referred to as hFE. This current gain hFE is calculated as the ratio of the collector current (IC) to the base current (IB) of the transistor when biased in the forward-active region (i.e., base-emitter junction forward biased, and collector-base junction strongly reverse-biased). This gain parameter thus essentially reflects the amplification effect of the transistor—a small change in the base current causes a proportionally larger change in the collector current, with hFE as the proportionality constant. Larger values of hFE are thus generally desirable for high performance circuits.
Another important measure relevant to bipolar transistor circuit behavior is the base-emitter voltage (VBE) of the transistor at a given collector current, in forward-active operation. Certain circuit arrangements, such as current mirrors and differential amplifiers, rely on matched performance of transistors relative to one another. A difference in VBE between paired transistors can establish an undesired offset voltage; in the context of a current mirror, the VBE offset appears as non-ideal matching of the collector currents of the mirror transistors (their bases being connected together).
As known in the art, bipolar transistor parameters, including forward-active current gain hFE and base-emitter voltage VBE, are affected by a number of design and manufacturing factors. Design factors include the desired dopant concentration in the emitter, base, and collector regions of the transistor, the desired physical dimensions of these regions, and the like. Physical factors also affect the variance of the transistor structure, as manufactured, from the transistor as designed, which is reflected in the transistor electrical parameters, including in the hFE and VBE values.
In many cases, the variance of the performance of a transistor as manufactured, from that expected of the transistor as designed, can be causally attributed to particular manufacturing processes. For example, variation in the implant dose and energy generally results in a predictable change in the dopant concentration and profile of the implanted region. However, the causal relationship between a manufacturing process and the resulting transistor performance parameter is not readily apparent in some cases. In some cases, the causal relationship between a process change and a widespread degradation in transistor performance can be quite puzzling.
It has been observed, in connection with this invention, that the hFE values of bipolar transistors in which one or more conductor levels overlying the bipolar transistors are formed of copper is significantly degraded, as compared with the hFE values of similar transistors for which aluminum is the metallization. It has also been observed, in connection with this invention, that the standard deviation of the hFE and VBE values of a population of bipolar transistors with copper metallization is significantly greater than the corresponding standard deviation of those values for transistors with aluminum metallization, indicating increased variation among transistors with copper metallization.
Degradation of transistor performance and increased variation in operating parameters are, of course, undesirable. However, some circuits are especially vulnerable to mismatch in device parameters among transistors within the same integrated circuit. As mentioned above, circuit mirrors and differential amplifiers are examples of circuits that rely on good matching of bipolar transistors with one another for optimum operation. A common measure of transistor mismatch is the standard deviation of the difference in a given parameter between pairs of transistors. For example, the standard deviation of the offset voltage (|VBE1−VBE2|) between two current mirror transistors in a population of current mirrors is a measure of the degree of device mismatch in that population, with smaller standard deviation desirable for stable and accurate circuit performance. It has been observed that the implementation of copper metallization not only degrades the circuit performance of bipolar transistors due to reduced transistor gain as mentioned above, but also increases transistor mismatch (in both the hFE and VBE values) among bipolar transistors in the same circuit.
By way of further background, the ion implantation of fluorine into the active regions of metal-oxide-semiconductor (MOS) transistors is known. Lin et al., “The Effect of Fluorine on MOSFET Channel Length”, Elec. Device Letters, Vol. 14, No. 10 (IEEE, October 1993), pp. 469-71, incorporated herein by reference, describes the implantation of fluorine into the source and drain regions of MOS transistors (i.e., specifically into the “lightly-doped drain” implanted regions) after formation of the polysilicon gate electrode; this paper reports that the fluorine results in a smaller channel length reduction, by retarding phosphorous lateral diffusion. Goto et al., “A Triple Gate Oxide CMOS Technology Using Fluorine Implant for System-on-a-Chip”, Digest of Technical Papers: 2000 Symposium on VLSI Technology, Paper 15.3 (IEEE, 2000), pp. 148-49, describes the implantation of fluorine into the low power CMOS active region, prior to formation of the gate oxide and gate electrode, to reduce gate leakage current.